The present invention relates to fabrication of metal oxide semiconductor (MOS) transistors, and in particular to a method for processing high-voltage MOS transistors.
High-voltage MOS transistors require a relatively thick gate oxide defined between adjacent source/drain regions, as compared with typical MOS transistors. For instance, a high-voltage MOS transistor may employ a gate oxide thickness of approximately 600 Angstroms (Å), whereas a typical MOS transistor may employ a gate oxide thickness of 100-150 Å or less. The thicker gate oxide, which is typically present over the source/drain regions, complicates lightly-doped-drain (LDD) implantation used to create the lightly-doped drain and source regions. The polysilicon gate is sufficient for typical MOS transistors to block LDD implantation in the channel region underlying the polysilicon gate. However, the higher energy LDD implantation required by the thicker gate oxide for high-voltage MOS transistors may result in LDD implantation beneath the polysilicon gate. This issue is resolved in the prior art by increasing the thickness of the gate polysilicon layer, which acts to block LDD implantation from the underlying channel region while creating the desired profile in the adjacent source/drain regions.
Increasing the thickness of the gate polysilicon region, however, adds to the overall topography (i.e., unevenness associated with the surface) of the device. The increased topography, from a practicality standpoint, precludes use of chemical-mechanical polishing (CMP) to planarize the subsequent pre-metal dielectric layers on the wafer. A resist etch back planarization process is used instead, but does not provide so planar a surface as the CMP process.
It would be beneficial for a fabrication process directed to high-voltage MOS devices, which require a relatively thick gate oxide layer, to also include a relatively thin polysilicon layer that is conducive to CMP planarization.